Embedding a deterministic RISC-V CPU inside Qwen 3.5 weights

On October 22, 2026, researcher Divyansh Agrawal released Qwenputer, an experimental modification of the stock Qwen 3.5 4B language model. This project embeds a fully deterministic 32-bit RISC-V CPU directly into the model’s weights, allowing it to execute code and perform arithmetic internally without relying on external runtimes or tool calls.

What happened

Agrawal modified the Qwen 3.5 4B architecture by compiling a RISC-V CPU into eleven additional layers placed in front of the model’s existing thirty-two layers. The resulting system, named Qwenputer, runs entirely within the forward passes of the neural network. It executes arithmetic operations, C code, and MicroPython scripts by leveraging the model’s internal state rather than calling out to a Python sandbox or external calculator.

The project demonstrates that hybrid models can host functional hardware simulations within their parameters. Agrawal also implemented an experimental in-model file storage system, allowing the model to save and retrieve text data across conversation turns. The code and model weights are available openly on GitHub, Hugging Face, and ModelScope, requiring only a single 24 GB GPU to run.

How it works

The core innovation relies on repurposing the Gated DeltaNet (GDN) attention layers found in Qwen 3.5. Three out of every four attention layers in this model use GDN, a linear recurrent neural network mechanism. Each GDN head maintains a state matrix that acts as memory. Normally, a gate value between zero and one causes this state to fade over time, enabling the model to forget irrelevant context. However, by setting the gate to exactly one and the write strength to one, the state becomes permanent and addressable.

Agrawal used one-hot key encoding to turn these GDN states into exact random-access memory (RAM). A one-hot key is a vector with a single active element, pointing to a specific row in the state matrix just like a memory address. When the model writes to this address, it completely overwrites the existing value rather than blending it. This allows the CPU to store registers, memory values, and program counters in the GDN state with perfect precision, avoiding the drift typical of standard attention mechanisms.

A custom compiler translates the RISC-V instruction set into transformer operations. Each CPU instruction, such as adding two numbers or jumping to a new line, is converted into a sequence of tokens generated by the model. These tokens include the memory address to write, the value to store, and a step marker. As Qwen generates these tokens during inference, the CPU effectively executes the program. The original Qwen weights remain untouched, with the computer logic added via extra dimensions and layers.

Key details

• The CPU is a 32-bit RISC-V core (RV32IM) with the Zba extension and a bignum unit, occupying eleven layers.
• It passed official riscv-tests and ran 18 million instructions free-running without a single error.
• On DeepMind arithmetic benchmarks, Qwenputer scored 97.5% on large division and multiplication tasks, matching or exceeding base Qwen with Python tools.
• The in-model filesystem supports up to 512 files, storing approximately 53,000 tokens of text in the DeltaNet state.
• The modified checkpoint size is 18.8 GB, roughly double the base model, due to zero padding in the added layers.
• Execution requires a small driver called RvChat to load firmware and manage trace tokens, preventing them from interfering with standard text generation.

Why it matters

For engineers building AI products, Qwenputer proves that large language models can achieve deterministic computation without external dependencies. Current systems often rely on tool calling, which introduces latency, security risks, and potential failure points when connecting to external APIs or sandboxes. By embedding the compute logic directly into the weights, the model ensures that arithmetic and logical operations are exact and self-contained. This approach eliminates the need for complex orchestration layers to manage external executors.

The project also highlights new avenues for AI safety and interpretability. Because the CPU’s state is stored in the GDN layers, it offers a transparent window into the model’s reasoning process. Researchers can monitor the exact values in the simulated RAM, providing a verifiable trail of execution that is difficult to hide or manipulate. This contrasts with standard chain-of-thought reasoning, which can be opaque or evasive. The ability to compile fixed monitors into the weights suggests a future where safety constraints are hard-coded into the model’s architecture rather than relying on prompt engineering.

What you can do

• Clone the Qwenputer repository from GitHub to access the experimental code and drivers.
• Download the model weights from Hugging Face or ModelScope using the Hugging Face CLI.
• Set up a local environment with uv and a single 24 GB GPU to run the chat interface.
• Use the provided RvChat driver to load the firmware and execute basic arithmetic queries.
• Experiment with the in-model filesystem by saving and retrieving text data across separate conversation sessions.
• Review the compiler code to understand how RISC-V instructions are mapped to transformer attention heads and feed-forward units.